상세 보기
Multi-Stack InTe Selector-Only Memory (SOM) Achieving Ultra-Low Power Operation (10 μa) and Excellent Endurance (∼ 1010 cycles)
- Seo, Yoori;
- Kim, Dongmin;
- Jung, Laeyong;
- Lee, Jangseop;
- Kwon, Ohhyuk;
- ... Lee, Tae-hoon;
- 외 3명
Citations
SCOPUS
7초록
We present an innovative In-Te based selector-only memory (SOM) featuring a multi-stack architecture that significantly boosts power efficiency and reliability. Through XPS, Raman spectroscopy and DFT simulation, we clarified how optimized In-Te bonding and trap engineering enable successful SOM operation while reducing write current (I<inf>write</inf>) to an ultra-low 10 μ A. This approach also resulted in a sufficient memory window (MW 1 V), minimized variability, and achieved excellent endurance (-1010 cycles). © 2025 JSAP.
- 제목
- Multi-Stack InTe Selector-Only Memory (SOM) Achieving Ultra-Low Power Operation (10 μa) and Excellent Endurance (∼ 1010 cycles)
- 저자
- Seo, Yoori; Kim, Dongmin; Jung, Laeyong; Lee, Jangseop; Kwon, Ohhyuk; Baek, Chanhwi; Park, Yu-bin; Lee, Tae-hoon; Hwang, Hyunsang
- 발행일
- 2025
- 유형
- Conference paper
- 저널명
- Digest of Technical Papers - Symposium on VLSI Technology
- 언어
- ENG
- 출판사
- Institute of Electrical and Electronics Engineers Inc.
- ISSN
- E 215-8968
P 0743-1562