A Power-Efficient Reconfigurable Hybrid CNN-SNN Accelerator for High Performance AI Applications

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초록

Deep learning-based object detection requires high computation, making real-time processing difficult due to excessive power consumption and irregular workloads in conventional accelerators. Event-driven hybrid model training has been explored as a method to reduce power consumption. However, its implementation on traditional hardware remains challenging due to the lack of efficient sparse computation optimization. To address this issue, this paper proposes a power-efficient CNN-SNN hybrid accelerator that leverages event-driven spiking computation and adaptive reconfiguration. Unlike conventional CNN accelerators that rely on continuous activation functions and fixed processing pipelines, the proposed architecture selectively converts energy-intensive layers into SNNs. This hybrid approach minimizes power-hungry multiply-accumulate operations by leveraging sparse, event-driven spike processing. The accelerator uses a reconfigurable dual-lane processor that switches between CNN and SNN operations for efficient workload distribution. To efficiently manage the dynamic switching between CNN and SNN operations, the accelerator employs adaptive dynamic memory optimization to minimize data movement overhead, while multi-stage pipeline optimizes temporal accumulation to maximize the benefits of event-driven SNN processing. The proposed hybrid CNN-SNN accelerator reduces power consumption by 32% while maintaining 97.5% accuracy, improving FPS per watt by 47-67% over conventional CNN architectures. Its dynamic workload adaptation increases inference speed by up to 16%, making it highly efficient for real-time edge AI.

키워드

Hybrid CNN/SNN accelerator; Low-power deep learning; Reconfigurable computing; Event-driven processing
제목
A Power-Efficient Reconfigurable Hybrid CNN-SNN Accelerator for High Performance AI Applications
저자
Yun, Heuijee; Park, Daejin
DOI
10.1109/COOLCHIPS65488.2025.11018586
발행일
2025
유형
Proceedings Paper
저널명
2025 IEEE SYMPOSIUM ON LOW-POWER AND HIGH-SPEED CHIPS AND SYSTEMS, COOL CHIPS