A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond

초록

In the latest technology nodes with complex design rules, it becomes highly-challenging to design standard cells (SDCs) by hand. To overcome this challenge, many studies have announced fully-automated SDC compilers for advanced nodes. However, previous studies cannot design SDCs that are beyond certain number of transistors or were requiring too expensive computing resources. Therefore, this paper provides highly compact Q-learning-based SDC compiler that 1) overcomes transistor count limitation of SDC design, and 2) can design SDCs (training and inferencing) on normal computing systems in less than day. In addition to 100% successful SDC designs, our SDC compiler optimizes the layout area of the most complex cell by up to 36.67% in the 3 nm technology node.

키워드