An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs)

초록

The Complementary FET (CFET) is known to be a potential device to continue the feature size scaling. However, studies forecast that increased parasitic RC neutralizes the area reduction advantage that CFETs can provide. In this paper, (1) we report that RC increase by CFETs is not that significant (only +4.25% compared to 5 track FinFET INV), and (2) propose a design methodology that optimizes the parasitics of CFET standard cells to make this happen. Our methodology shows improvements in parasitics by up to 8.15% for capacitance and 32.73% for resistance when comparing the two types of CFET structures.

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