Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design

초록

The predicted end of scaling and the exponential increase of user data in the era of the connected world are asking whether the current binary systems in CMOS can successfully provide solutions to the expected challenges. Regarding these challenges, ternary systems are showing a high potential to provide solutions to these known issues. In detail, the tunnelling-based MOSFET (T-CMOS) is reported as promising compared to any other ternary devices studied. However, despite the potential, studies lack how a complete system can be designed in actual T-CMOS-based circuitry. Therefore, in this paper, we provide a holistic study of how T-CMOS-based circuits can be designed. In detail, 1) we provide a pathway to designing a balanced ternary full adder and provide the fundamental of how combinational ternary logic can be designed in T-CMOS. 2) We present various sequential ternary logic based on T-CMOS. 3) We present various circuit techniques that could enhance the performance of combinational and sequential ternary logic. Based on our study, we provide the first balanced ternary adder that the transistor count is only 42 and enhance the operating frequency of the T-CMOS-based ternary system by 5.6 × to 58.5 × . © 2004-2012 IEEE.

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