An RTL-Based General Synthesis Methodology for Device-Independent Ternary Logic Circuits

초록

Ternary logic circuits are considered a high-potential alternative that can continue the technological advance of binary logic. Current studies in ternary logic focus on two aspects: One focuses on designing specific ternary circuits (such as adders, multipliers, and CPUs), and the other proposes design methodologies that make circuit design possible on targeted ternary devices. However, the implementation of large-scale ternary logic requires hardware description language (HDL) and a synthesis methodology that can be applied to various ternary devices. Thus, this study proposes 1) a methodology of ternary RTL-to-gate-level netlist synthesis, 2) a syntax for ternary logic based on Verilog HDL, and 3) the first GT-LOGIC (generic ternary logic) library and mapping strategy for logic synthesis in our synthesis process. Our first RTL-level synthesis method reports that our synthesized netlist shows 63.39% reduced cell count on average compared to the previous MUX-based synthesis. In addition, we emphasize that our methodology successfully synthesizes ternary logic in various ternary devices such as Memristor-based CMOS, CNTFET, T-CMOS, and DEPFET.

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