Three-dimensional contact resistance model based on tri-layer transmission line method for precise analysis of scaled FinFET source/drain contacts

초록

The effects of source/drain (S/D) contact resistance on scaled transistors are becoming increasingly significant because contact resistance is inversely proportional to the contact area. Thus, precise evaluation of contact resistance is crucial for the design and analysis of scaled transistors, especially non-planar three-dimensional field-effect transistors (3D FETs) with multi-fin or gate-all-around (GAA) architectures for sub-10 nm technologies. For several decades, contact resistance has been modeled and evaluated using the transmission line model (TLM), which was originally designed for planar devices. However, the conventional TLM, a 2D model, cannot be directly applied to scaled 3D FETs because this model assumes no current density along the vertical direction in the S/D regions. In this study, we propose a 3D contact resistance model that can precisely analyze the S/D contact resistance of scaled FinFETs with raised S/D structures. This model is developed based on a modified tri-layer TLM to account for both the complicated lateral and vertical current density components within the metal-semiconductor interface and the raised S/D regions. The accuracy of the proposed model is validated by comparing contact resistances obtained from the developed model with TCAD simulation results across various 3D S/D structures. The model exhibits good agreement with the simulation results, with deviations of less than 2% under various contact conditions determined by contact length and specific contact resistance. This 3D contact model provides an effective framework for designing and analyzing the contact properties of scaled transistors, such as FinFETs and GAA-FETs.

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