FPGA Realization of Lane Detection Unit using Sliding-based Parallel-Segment Detection for Buffer Memory Reduction

초록

With the development of various chips, such as VLSI chips, and the development of semiconductor technology and artificial intelligence, autonomous driving technology is advancing daily. Lane recognition technology, which can be considered the most important in the implementation of autonomous vehicles, requires a large amount of computation and processing time because data must be received from a camera attached to the vehicle and processed in real time. To design a more efficient and implementable lane recognition algorithm, we proposed a method to reduce the usage of buffer memory by using parallel operation. Most of the boards used in autonomous vehicles are lightweight, so the lane recognition algorithm is also lightweight to use a minimum library. First, after reading the image, canny edge-detection is executed through grayscale conversion, Gaussian smoothing, a Sobel operator, non-maximum suppression, and hysteresis in parallel. The lane is inspected using the Hough transform as an input to the image with the edge detected by canny edge-detection. Due to parallel operation's nature, the effect is insignificant when a single image input is received, but the operation is more efficient when multiple images are input in real time. We used a relatively low-level C language for efficiency and processed images with loops and operations.

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