A Low Latency Approximate Adder Design Based on Dual Sub-Adders With Error Recovery

초록

This paper presents a novel dual sub-adder based approximate adder that splits a precise adder into two to significantly reduce the latency. The proposed error recovery and reduction technique effectively compensates for the catastrophic accuracy degradation incurred by the split. Implemented in a 65-nm CMOS technology, our design reduces the delay and energy consumption by up to 68% and 78%, respectively, compared to a traditional adder, and outperforms other existing approximate adders in hardware and accuracy joint metrics. The proposed design's efficacy is shown through digital image processing applications where our design makes processed output images closest to the one using the accurate adder over other approximate adders. Furthermore, the proposed design is proven to be a general adder model that can be employed in existing approximate adders to enhance hardware resource and error characteristics considerably.

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