Structurally optimized SiC CMOS FinFET for high-temperature and low-power SoC logic integration

초록

A high-temperature-operable binary inverter was designed through structural optimization of SiC-based CMOS FinFETs using 3D TCAD simulations. A FinFET architecture was incorporated into SiC CMOS with an optimized fin structure to overcome the critical challenges of high subthreshold swing (SS) and threshold voltage (Vth) inherent in planar MOSFET-based SiC CMOS technology, thus achieving a high-performance logic system. Subsequent structural optimization led to Vth values of 1.83 and 2.54 V for the n-type and p-type FinFETs, respectively, along with substantially enhanced SS values of 73.33 and 77.74 mV/decade, respectively. Additionally, to validate the applicability of SiC CMOS FinFETs to high-temperature environments compared to conventional Si CMOS FinFETs, the self-heating characteristics, as well as the temperature-dependent behavior of Vth and SS, were analyzed up to 700 K. Finally, a binary inverter was designed based on the optimized FinFETs. The circuit operated at a low supply voltage of 3.3 V and achieved a noise margin of 0.820 V (0.249 VDD) with a maximum gain of 13.3 at 300 K. Especially, it maintained stable operation with a noise margin of 0.811 V (0.246 VDD) and a gain of 5.80 even at 700 K. These results confirmed its robustness and potential for next-generation logic systems and high-temperature CMOS applications.

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