A Light-Weight AES Design using LFSR-based S-Box for IoT Applications

초록

This paper presents a novel light-weight AES architecture based on linear feedback shift register (LFSR). Since the traditional substitution-box (S-box) of the AES architecture consumes a large amount of hardware resources, we propose LFSR-based S-box and inverse S-box designs to reduce the hardware overheads significantly. In addition, we replace the conventional AES key scheduler with the LFSR-based round key generator to improve the hardware efficiency further. When implemented in a 32-nm CMOS technology, the proposed designs improve the area, delay, power, and energy by 57.4%, 64.3%, 30.1%, and 75% in the AES-128, 52.2%, 12.5%, 21.9%, and 31.7% in the AES-192, and 54.8%, 5.2%, 23.4%, and 27.4% in the AES-256, respectively, when compared to the traditional S-box based AES architecture. In addition, a joint analysis of our designs in terms of area, delay, and energy shows that the proposed AES designs enhance the area-delay product (ADP) and energy-delay product (EDP) by up to 84.7% and 82.5%, respectively, compared to the traditional design.

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