Hardware implementation of the coding algorithm based on FPGA

초록

In this article, the efficient implementation multiplier of polynomials irreducible polynomials modulo for cryptographic encryption and decryption using FPGA is presented. For this, the Nexys 4 board based on the Artix-7 Field Programmable Gate Array (FPGA) from Xilinx was chosen. Verilog HDL is used to describe the circuit for reducing a number modulo. The results of a timing simulation of the device are presented in the form of time diagrams for a given 8-bit number, confirming the correct operation of the device. The developed encryption algorithm on the basis of non-positional polynomial notations is intended for software, hardware, and also software and hardware implementation. The main hardware-implemented device in non-positional algorithm of the cryptographic transformation is a device for the multiplication of polynomials irreducible polynomials modulo, which produces routine calculations on data encryption. These mathematical operations are computationally intensive and fundamental arithmetic operations, which are intensively used in many fields such as cryptography, number theory, and finite field arithmetic. © Published under licence by IOP Publishing Ltd.