Design of Approximate Floating-Point Arithmetic Units Using Hardware-Efficient Rounding Schemes

초록

This letter presents novel approximate floating-point arithmetic units that leverage hardware-efficient rounding schemes to enhance computational accuracy while significantly improving hardware efficiency. By eliminating the need for guard, round, and sticky bits, the proposed designs achieve substantial reductions in area, power, delay, and energy up to 42.3%, 32.1%, 39.3%, and 58.8%, respectively, compared to conventional exact floating-point units implemented in a 28-nm CMOS technology. Experimental evaluations across multiple applications, including image processing, convolutional neural networks (CNNs), and spiking neural networks (SNNs), demonstrate that the proposed approach maintains high computational accuracy. Evaluations across image processing and neural network tasks show minimal quality and accuracy degradation, confirming the suitability of the proposed designs for energy-efficient applications. © 2009-2012 IEEE.

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