Optimization of One-transistor (1T) DRAM Using Device Parameters-dependent Zero-temperature Coefficient Point

초록

In this study, we present a design technique that minimizes drain current fluctuations due to temperature changes and utilizes the concept of zero-temperature coefficient (ZTC) points to increase the stability of the onetransistor (1T) DRAM operation. In particular, the reliability of temperature changes was secured by maintaining the stability of drain current in a high temperature (300 K-400 K) environment through optimization of ZTC operation voltage, and data retention time and stability were strengthened by applying an asymmetric dual-gate structure. In addition, by optimizing the size of the device and adjusting the main gate work function (WF1) and body doping concentration, stable data retention performance was confirmed even in a high temperature environment. These designs minimize leakage current and maintain data retention times up to 330 ms to ensure reliable memory operation under various environmental conditions.

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