Lightweight Buffer Insertion for Clock Tree Synthesis Visualization

초록

Important element of ASIC or SoC design is clock synchronization. Theoretically, It is assumed that all state element is used the same clock signal.[3] In fact, clock asynchronization occurs due to gate delay, propagation delay, wire length, etc. Until the clock reaches the state element, delay occurs. Since this difference occurs, the CTS is an essential factor. Buffer insertion is an essential element in using CTS, which reduces delay and maintains signal integrity. The purpose of CTS is to attain clock minimum skew, and the most important thing in the CTS process is to know the accurate delay and skew information. In this paper, we focus on minimized clock skew and emphasize the efficient buffer insertion algorithm of CTS. It use C language on Visual Studio to calculate delay and after buffer insertion. Graphviz is open-source graph visualization software. Graph visualization is a way of representing structural information as diagrams of abstract graphs and networks. This paper is used to visualize Tree structure. After debugging C language,.dot file is produced and Graphviz using dot language executes.

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