A Novel Efficient Approximate Adder Design using Single Input Pair based Computation

초록

This paper proposes a novel approximate adder that exploits only a single input pair for approximation using a few logic gates. The mean error distance (MED) and mean relative error distance (MRED) of our adder are significantly better than those of other approximate adders considered herein. With a 65nm CMOS technology, the proposed design also achieves 21% and 12% improvements in area and power, respectively, in comparison to other approximate designs. Moreover, our adder shows higher image quality in digital image processing than other approximate adders while consuming similar hardware costs.

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