Hardware-Efficient Quantized Stochastic Computing With Reduced Precision Stochastic Number Generator and LFSR-Based Counter

초록

Stochastic computing (SC) is an emerging computing paradigm that offers excellent hardware efficiency and error tolerance. However, adopting SC in practical applications is not straightforward but faces serious challenges. In particular, a considerable overhead is imposed by the conversion between binary number and stochastic counterpart, which is usually performed by a stochastic number generator (SNG) and a binary counter. In this paper, we address this overhead issue by introducing a novel quantized SC architecture that shrinks the SNG hardware complexity significantly and a new approximate binary counter. To do this, we quantize binary numbers for SNGs to lower precision counterparts through several bit truncation schemes, which leads to an SNG overhead reduction. Also, we exploit a small-sized linear feedback shift register (LFSR) in the binary counter design to reduce its hardware resource consumption. When implemented in a 65-nm CMOS technology, the proposed quantized SNG and approximate binary counter reduce area and power by up to 68.3% and 80.6%, respectively, compared to the conventional full-precision SNG with an accurate counter. In addition, the proposed SC architecture with the LFSR-based counter does not deteriorate the stochastic computation accuracy beyond a certain degree of quantization. Besides, we demonstrate that the proposed SC schemes negligibly impact on processing quality with remarkably improved hardware efficiency by adopting it in a digital image processing application.

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