Hardware Acceleration of Real-Time LiDAR Packet Decoding and Reconstruction via Parallelism

Citations

SCOPUS

1

초록

Light detection and ranging (LiDAR) sensors deliver precise depth information and maintain satisfactory performance even under adverse weather conditions, making them essential for perception in three-dimensional space. LiDAR sensors generate millions of points per second; however, achieving real-time processing requires fast and seamless preparation of point-cloud data formatted for deep learning models. In this paper, we introduce a fast, yet efficient hardware design that decodes LiDAR data packets and reconstructs point cloud into the IEEE 754 half-precision floating-point (FP16) format utilizing inherent parallelism in packet decoding. In terms of processing time for a single LiDAR packet, our Ultra96-V1 FPGA-based implementation outperforms the state-of-the-art software-based approach by 1.42×, on average, and generates floating-point data faster by 3.68 × with better power efficiency by 20.4% than the state-of-the-art FPGA-based solution while maintaining the range difference within an acceptable range. © 2009-2012 IEEE.

키워드

data reconstruction; hardware acceleration; LiDAR; packet decoding; real-time processing
제목
Hardware Acceleration of Real-Time LiDAR Packet Decoding and Reconstruction via Parallelism
저자
An, Taehyeon; Kong, Joonho
DOI
10.1109/LES.2025.3632806
발행일
2025
유형
Article in press
저널명
IEEE Embedded Systems Letters