An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector

초록

An output-capacitor-free NMOS digital LDO (DLDO) using gate driving strength modulation (GDSM) is described. The proposed DLDO is mainly based on the timedriven topology while the GDSM changes the gate driving level adaptively according to the load current condition. The proposed GDSM lowers the gate driving level in the light load condition which improves the load transient response, widens the load current dynamic range, and reduces the output voltage ripple. A droop detector combined with the modulation scheme is also proposed to further improve the undershoot and recovery time. The proposed DLDO has been implemented in 28 nm CMOS and the 20,000x load range is obtained even with 256 unity power switch arrays. When the load current changes from 5 mA to 85 mA, the V-OUT droop and recovery time are 130 mV and 2.5 mu s, which are 4.92x and 70x improvements compared to the baseline time-driven DLDO, respectively.

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