A Haar Classifier Accelerator with Reduced Multiplexer Usage

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초록

A Haar classifier accelerator is widely used in embedded vision systems because it can detect faces rapidly and accurately. However, implementing the Haar classifier accelerator requires considerable hardware resources, many of which are multiplexers used to extract integral values within a sub-window. Therefore, to decrease the multiplexer usage in the Haar classifier accelerator, we propose a method that reduces the sub-window size by excluding some rows and columns of the sub-window from integral value extraction. The proposed method considerably reduces the multiplexer usage than that of the conventional method while maintaining the detection rate and the number of false detections.

키워드

face detection; Haar classifier accelerator; FPGA
제목
A Haar Classifier Accelerator with Reduced Multiplexer Usage
저자
Lee, SangHyun; Moon, Byungin
DOI
10.1109/ISOCC53507.2021.9613971
발행일
2021
유형
Proceedings Paper
저널명
18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021)
페이지
399 ~ 400