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Minimizing Input Current Ripple for Four-Phase Input-Parallel Output-Series DCDC Converter With Phase-Shift Modulation
- Van Bui, Dai;
- Cha, Honnyong
Citations
WEB OF SCIENCE
19Citations
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26초록
This letter proposes a pulse width modulation (PWM) scheme based on phase-shift modulation for the four-phase input-parallel output-series (4P-IPOS) converter. And operation with dual-output configuration is investigated. The natural output voltages and inductor currents balancing can be achieved even without any extra components or dedicated control. In addition, compared with the conventional PWM scheme, performance improves. The input current ripple is reduced significantly at high voltage gain. An 800-W prototype of the 4P-IPOS converter was built and tested to verify the performance of the suggested scheme.
키워드
Current balancing; input-parallel output-series (IPOS) converter; pulsewidth modulation (PWM); ripple cancellation; voltage balancing; ASYMMETRICAL PWM SCHEME; HIGH STEP-UP; BOOST CONVERTER; DC/DC CONVERTER
- 제목
- Minimizing Input Current Ripple for Four-Phase Input-Parallel Output-Series DCDC Converter With Phase-Shift Modulation
- 저자
- Van Bui, Dai; Cha, Honnyong
- 발행일
- 2023-07
- 유형
- Article
- 권
- 38
- 호
- 7
- 페이지
- 8005 ~ 8010
- 언어
- ENG
- 출판사
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- 발행국가
- 미국
- 분량
- 6 페이지
- ISSN
- E 1941-0107
P 0885-8993