Minimizing Input Current Ripple for Four-Phase Input-Parallel Output-Series DCDC Converter With Phase-Shift Modulation

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WEB OF SCIENCE

19
Citations

SCOPUS

26

초록

This letter proposes a pulse width modulation (PWM) scheme based on phase-shift modulation for the four-phase input-parallel output-series (4P-IPOS) converter. And operation with dual-output configuration is investigated. The natural output voltages and inductor currents balancing can be achieved even without any extra components or dedicated control. In addition, compared with the conventional PWM scheme, performance improves. The input current ripple is reduced significantly at high voltage gain. An 800-W prototype of the 4P-IPOS converter was built and tested to verify the performance of the suggested scheme.

키워드

Current balancing; input-parallel output-series (IPOS) converter; pulsewidth modulation (PWM); ripple cancellation; voltage balancing; ASYMMETRICAL PWM SCHEME; HIGH STEP-UP; BOOST CONVERTER; DC/DC CONVERTER
제목
Minimizing Input Current Ripple for Four-Phase Input-Parallel Output-Series DCDC Converter With Phase-Shift Modulation
저자
Van Bui, Dai; Cha, Honnyong
DOI
10.1109/TPEL.2023.3264792
발행일
2023-07
유형
Article
저널명
IEEE Transactions on Power Electronics
권
38
호
7
페이지
8005 ~ 8010