Multi-Threaded Data-Scrambling Techniques Using Reduced on-Chip Memory for Light-Weight Embedded Systems

초록

With the increasing importance of data acquisition and processing in various applications, it is essential for systems using reduced memory to efficiently fulfill these requirements. In this study, we propose a method for high-speed data acquisition and signal processing in reduced memory by utilizing an ARM Cortex-M3-based STM32F103 Nucleo board. The proposed system consists of an analog-to-digital converter (ADC), two buffers (Buffer1 and Buffer2), and a universal asynchronous receiver/transmitter (UART) module, and the four modules are threaded to optimize the process of data acquisition, signal processing, and data transmission. We set the ADC and signal processing to operate at maximum speed and used minimal memory in the process. Our results show that the proposed system can effectively collect and process data using reduced memory in embedded systems. © 2024 IEEE.

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