Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation

초록

This paper proposes a new approximate adder that increases the accuracy of addition while ensuring acceptable hardware performance. The proposed adder implemented with a 32-nm CMOS technology reduces the area, power, and delay by 40%, 43%, and 50% of those of the traditional accurate adder, respectively. Moreover, the proposed adder shows a better tradeoff performance than the existing approximate adders considered in this paper when jointly evaluating both accuracy and hardware performance. Specifically, the proposed adder enhances power-mean relative error distance (MRED) product, energy-MRED product, and area-MRED product by up to 65%, 65%, and 64% compared to the approximate adder considered herein.

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