Fast Bit Inversion Vulnerability Pre-estimation using Tcl and UPF in RTL Simulation Runtime

초록

As more of the world's information is digitized, it becomes increasingly important for the bits constituting the data to have integrity. Because bit errors are corrected and detected by the error correcting code module that can burden the entire system, it must be positioned only where it is needed. Therefore, it is necessary to detect places vulnerable to bit inversion error, when encoding and decoding ECC. However, the reproduction of bit inversion error cannot be deterministically described at the register transfer level (RTL) design stage, and it is difficult to find it at the RTL simulation stage. In this paper, we propose a structure that uses Tcl and unified power format (UPF) together to solve the above problem at the RTL design stage and verify the structure using a tiny processing unit (TPU). In order to find out vulnerabilities in RTL design based on the module-specific power which is derived from inserted bit inversion, we utilized the Tcl file to insert inversion error into simulation runtime and UPF to identify the power of each module. Also to validate vulnerabilities at simulation runtime, we accelerated the simulation. We branch the simulation by saving and loading the snapshot, which reduces unnecessary repetitive motions during multiple simulation times. Through this process, we verified 40% time reduction of simulation time. © 2023 IEEE.

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