Resilient event-triggered quasi-synchronization control for CLSs with parameter mismatches under DoS attacks

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초록

This paper investigates quasi-synchronization of chaotic Lur’e systems (CLSs) with parameter mismatches under denial-of-service (DoS) attacks. A resilient memory event-triggered scheme (RMETS) is proposed to mitigate network congestion and attack-induced disruptions. Unlike conventional schemes requiring prior knowledge of attack timing, RMETS employs an acknowledgment (ACK) mechanism to detect packet loss and introduces an ACK-related performance loss term for adaptive adjustment of release probability. Historical release data are further incorporated to refine control updates at critical sampling instants, balancing communication demands with control performance. A co-design of RMETS and a memory-based controller ensures the quasi-synchronization of CLSs within a predefined error bound. The effectiveness of the proposed approach is validated through simulations using Chua’s circuit. © 2025 International Society of Automation. Published by Elsevier Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies.

키워드

Chaotic Lur’e systems; DoS attacks; Quasi-synchronization; Resilient memory event-triggered scheme; CHAOTIC LURE SYSTEMS; MASTER-SLAVE SYNCHRONIZATION; SAMPLED-DATA SYNCHRONIZATION; EXPONENTIAL SYNCHRONIZATION; NETWORKS; CRITERIA
제목
Resilient event-triggered quasi-synchronization control for CLSs with parameter mismatches under DoS attacks
저자
Xu, Dong; Liu, Yajuan; Lee, S. M.; Xie, Xiangpeng
DOI
10.1016/j.isatra.2025.09.027
발행일
2025-12
유형
Article
저널명
ISA Transactions
권
167
페이지
1085 ~ 1092