A DVS-Enabled Distributed Digital LDO Providing Rapid Uniform Power Grid and Ripple Reduction Achieving 20.1-ps FOM in 28 nm CMOS

초록

A dynamic voltage scaling (DVS) enabled distributed digital low-dropout voltage regulator (LDO) is described. The proposed distributed LDO utilizes a multi-point average sensing to enable rapid and uniform output voltage regulation across a large-scale power grid, even during unbalanced load transients. A 16-bit thermometer-code flash analog-to-digital converter (FADC) combined with unary passgate configurations and an adaptive on-resistance (R-ON) modulation is employed to ensure a small output voltage ripple during DVS operation, using only a small 13.4nF output capacitor. The proposed distributed LDO has been implemented in 28nm CMOS, achieves a 10.4A/mm(2) current density, 99.96% current efficiency, and a 20.1ps FOM. It has also been tested under various unbalanced load transient conditions and can rapidly regulate the output voltage back to the target level.

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